Methods and apparatuses for peak detection among multiple signals

ABSTRACT

Digital peak detection among multiple signals, or inputs. In one embodiment, a detection method that includes receiving multiple digitized input signals. For each digitized input signal, the method also includes noting a first data value associated with the digitized input signal at a first time. The method includes comparing the first data values to determine a largest first data value from among the first data values. For each digitized input signal, the method includes noting a second data value associated with the digitized input signal at a second time. The method includes comparing the second data values to determine a largest second data value from among the second data values. The method includes comparing the largest second data value with a threshold data value. The method includes detecting a peak when the largest second data value is greater than the threshold data value, and less than the largest first data value. In other embodiments, devices that includes a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) that is configured to perform at least the steps of this detection method. That is, the FPGA or the ASIC can be provided with logic, or programming, that can be utilized in performing the steps of this detection method.

This application claims priority to U.S. Provisional Patent ApplicationSer. No. 60/344,933, filed Dec. 31, 2001. This provisional applicationis incorporated by reference.

REFERENCE TO APPENDIX

This application includes a computer program listing appendix, submittedon compact disc (CD). The content of the CD is incorporated by referencein its entirety and accordingly forms a part of this specification. TheCD contains the following files: File name: full7function.txt File Size:25.3 kb File name: eachchannel.txt File Size: 5.53 kb Creation date forCD: Dec. 31, 2002

BACKGROUND OF THE INVENTION

The portion of this disclosure contained on CD of this patent documentcontains material that is subject to copyright protection. The copyrightowner has no objection to the facsimile reproduction by anyone of thepatent document or the patent disclosure on the CD, as it appears in thePatent and Trademark Office patent files or records, but otherwisereserves all copyright rights whatsoever.

1. Field of the Invention

The invention relates generally to the field of electronic detection.More particularly, the invention relates to peak detection. Even moreparticularly, the inventions relates to methods and apparatuses thatprovide digital peak detection among multiple signals.

2. Discussion of the Related Art

In electronic detection applications, it may be necessary to find andrecord pulse peaks from continuous streams of analog signals. Thestreams of analog signals may be, for example, amplified laser detectoroutputs, or the like. In analog detectors, a front-end amplifiercircuitry has been used to deliver high level analog signals to thebalance of a detection circuit. A commonly employed analog peak findingtechnique includes utilizing a biased diode matrix to find the largestinput signal among the various input channels. A digital follow-oncircuit for pulse amplitude recording and transmission has also beenused.

A problem with this technology has been the small instantaneous dynamicrange of the analog detection circuit, typically of the order of 20 to1, which prevents it from being able to track widely varying signals.Therefore, what is required is solution that provides a wideinstantaneous dynamic range.

Another problem with this technology has been that the very high speedemitter coupled logic (ECL) parts needed for the peak detection andcapture functions dissipate a substantial amount of power. Therefore,what is also needed is a solution that can operate with low powerdissipation.

The following U.S. patents are representative of aspects of the state oftechnology relating to electronic detection.

U.S. Pat. No. 6,424,900, which is incorporated by reference, involves apartial discharge measurement system is provided which comprises adigital peak detection circuit. The partial discharge measurement systemdigitizes and detects both positive and negative slopes of a signal froman electrical device being tested. The partial discharge measurementsystem controls the shape of pulse capture windows in accordance withdifferent modes of operation, and controls the timing of pulse datacapture depending on the mode of operation and the polarity of thesignal.

U.S. Pat. No. 6,215,335, which is incorporated by reference, involves apeak detector that compares an input signal to a first reference voltageto produce a maximum sample signal, and compares the input signal to asecond reference voltage to produce a minimum sample signal, wherein themaximum and minimum sample signals produce a sampling of the currentinput signal thereto to produce a maximum output signal and a minimumoutput signal, respectively. The detector compares the previouslyretrieved input signal value with a current input signal value. Thecurrent input signal is used as the maximum output signal if it isgreater than a previous maximum output signal and providing the currentinput signal as the minimum output signal if it is less than a previousminimum output signal. The output provides signal level and offsetsignal information which, when gated with a predetermined clock signal,produces nonoverlapping phased output signals.

U.S. Pat. No. 5,920,438, which is incorporated by reference, involves aprogrammable digital device and method for generating tracking thresholdsignals for qualification of input peak signals in response toprogrammed digital gain signals which control the rate at which theenvelope of the qualified input peak signals is followed, and inresponse to a programmed digital attenuation signal which determines theproportion of the peak envelope at which to generate new trackingthreshold signals. The programmable digital device and method alsoprovide a programmed clamp signal to clamp the positive and negativethreshold signals to not fall below the programmed values. An anti-hangcapability is provided to allow the thresholds to drop after aprogrammed time period during which no signal is detected. In analternative arrangement, the centerline of the envelope is followed andused as the threshold.

U.S. Pat. No. 5,631,592, which is incorporated by reference, involves apulse generation and sensing arrangement in a microprocessor system(100—this and the other numbers in this paragraph are taken from U.S.Pat. No. 5,631,592) includes an input/output terminal (130) whichreceives an input signal or produces an output signal, an edge detector(132) which senses pulse edges in the input signal, timers (108, 110)which produce time values, registers (120, 124, 126) which hold timevalues produced by the timers corresponding to edges detected by theedge detector or which hold values corresponding to pulse edges to begenerated, comparators which compare the values held in the registerswith time values produced by the timers, and a flip-flop (128) forgenerating a signal whose state changes in response to the comparators.The arrangement allows the generation and/or sensing of signals withshort pulse widths and a wide range of duty cycles, and minimizessoftware overhead. A continuous PWM signal may be generated withoutfurther software involvement after initial writing of edge values.

The shortcomings described above are not intended to be exhaustive, butrather among the many that tend to impair the effectiveness ofpreviously known techniques of detecting the peak pulse from multipleinputs. Other noteworthy problems may also exist; however, thosementioned here are sufficient to demonstrate that methodologiesappearing in the art have not been altogether satisfactory.

SUMMARY OF THE INVENTION

The shortcomings listed above are reduced or eliminated by the presenttechniques. These techniques are applicable to a vast number ofapplications, including but not limited to applications involving laserdetection.

In one respect, the invention is a detection method. The method includesreceiving multiple digitized input signals. For each digitized inputsignal, the method also includes noting a first data value associatedwith the digitized input signal at a first time. The method includescomparing the first data values to determine a largest first data valuefrom among the first data values. For each digitized input signal, themethod includes noting a second data value associated with the digitizedinput signal at a second time. The method includes comparing the seconddata values to determine a largest second data value from among thesecond data values. The method includes comparing the largest seconddata value with a threshold data value. The method includes detecting apeak when the largest second data value is greater than the thresholddata value, and less than the largest first data value.

The method may also include extracting the second data values once thepeak is detected, and storing them in a memory device, which may, forexample, be a first-in-first-out memory device, or the like. Thecomparing of the first data values may take place over multiple clockperiods. Similarly, the comparing of the second data values may takeplace over multiple clock periods.

The method may also include first digitizing multiple analog inputsignals to get the multiple digitized input signals that are thenreceived, and filtering the multiple digitized input signals.

In another respect, the invention is a computer readable mediumcomprising machine readable instructions for implementing the detectionmethod described above.

In still other respects, the invention is a device that includes eithera field programmable gate array (FPGA) or an application specificintegrated circuit (ASIC) that is configured to perform at least thesteps of the detection method described above. That is, the FPGA or theASIC can be provided with logic, or programming, that can be utilized inperforming the steps of the detection method described above.

These and other embodiments of the invention, along with associatedadvantages, will be better appreciated and understood when considered inconjunction with the following description and the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings demonstrate certain aspects of the presentmethods and devices. They illustrate by way of example and notlimitation.

FIG. 1 is a flowchart of a processing method for an FPGA that can bepart of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention.

FIG. 2 is a spreadsheet showing a processing layout for an FPGA that canbe part of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention.

FIG. 3 is a spreadsheet showing a processing layout for an FPGA that canbe part of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention in which 2input signals are compared.

FIG. 4 is a spreadsheet showing a processing layout for an FPGA that canbe part of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention in which 7input signals are compared.

FIG. 5 is a spreadsheet showing a processing layout for an FPGA that canbe part of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention in which 19input signals are compared.

FIG. 6 is a spreadsheet showing a breadboard simulation according to oneembodiment of the present invention in which 2 signals are compared.

FIG. 7 is a chart graphically depicting data from FIG. 6.

DESCRIPTION OF ILLUSTRATED EMBODIMENTS

In this document (including the claims), the terms “comprise” (and anyform of comprise, such as “comprises” and “comprising”), “have” (and anyform of have, such as “has” and “having”), and “include” (and any formof include, such as “includes” and “including”) are open-ended linkingverbs. Thus, a detection method “comprising” (a) receiving multipledigitized input signals; (b) for each digitized input signal, noting afirst data value associated with the digitized input signal at a firsttime; (c) comparing the first data values to determine a largest firstdata value from among the first data values; (d) for each digitizedinput signal, noting a second data value associated with the digitizedinput signal at a second time; (e) comparing the second data values todetermine a largest second data value from among the second data values;(f) comparing the largest second data value with a threshold data value;and (g) detecting a peak when the largest second data value is: (i)greater than the threshold data value, and (ii) less than the largestfirst data value, is a detection method that possesses these steps, butis not limited to possessing only these steps. For example, such adetection method also covers a method that includes (h) extracting thesecond data values; and (i) storing the second data values in a memorydevice.

Similarly, a device “comprising” an application specific integratedcircuit (ASIC) configured to perform steps (a)-(g) referenced above is adevice that possesses such an ASIC, but is not limited to possessingonly such an ASIC nor is the referenced ASIC limited to one thatperforms only those steps.

The terms “a” and “an” are defined as one or more than one. The term“another” is defined as at least a second or more. The term “coupled” isdefined as connected, although not necessarily directly, and notnecessarily mechanically.

The invention and its various features and advantageous details areexplained more fully with reference to the nonlimiting embodiments thatare illustrated in the accompanying drawings and detailed in thefollowing description. Descriptions of well known starting materials,processing techniques, components and equipment are omitted so as not tounnecessarily obscure the invention in unnecessary detail. It should beunderstood, however, that the detailed description and the specificexamples, while indicating exemplary embodiments of the invention, aregiven by way of illustration only and not by way of limitation. Varioussubstitutions, modifications, additions and/or rearrangements within thescope of the invention will become apparent to those skilled in the artfrom this disclosure.

The invention provides methods and apparatuses for finding, recording,and transmitting pulse peaks from a continuous stream of digitizedanalog signals in real-time. The input analog signals may include, forexample, amplified laser detector outputs. As a result of the presentmethods and apparatuses, a high instantaneous dynamic range is achieved,and significant reductions in cost, space and heat dissipation areafforded over previously known techniques.

In one embodiment, the methods and apparatuses of the invention canprovide an effective data bandwidth on the order of 20 nanoseconds,i.e., consecutive pulses separated by 20 nanosecond intervals can bedetected and stored using the present methods and apparatuses. However,smaller intervals may be achieved with a higher sampling rate in theanalog to digital conversion.

In another embodiment, the methods and apparatuses of the invention canprovide an instantaneous dynamic range on the order of 100 to 1, i.e.,very large instantaneous signal magnitude variations can be detected.However, a higher instantaneous dynamic range may be achieved withhigher-resolution analog to digital converters.

The invention can be implemented in a method or apparatus that utilizesthe programming in an FPGA, sometimes called a programmable logic device(PLD), or the like. The invention can also be implemented in a method orapparatus that utilizes an ASIC.

In an embodiment of the invention in which a method or apparatusutilizes the programming in an FPGA, two or more channels of digitaldata, which may be taken from one or more analog to digital converter(ADC) circuits, are fed into the input pins of the FPGA. The channels ofdigital data, also referred to herein as multiple digitized inputsignals, may be 2 or greater in number, including 2, 3, 4, 5, 6, 7, 8,9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or more. The data that is fedinto the input pins of the FPGA is latched into registers internal tothe FPGA, with a new data word input on each channel appearing at eachnew rising edge of the clock.

Referring to aspects of the same embodiment, each data from eachdigitized input signal is first passed through a high-pass filter, i.e.,filtered, in order to eliminate the small but random offsets that may begenerated in each ADC circuit. This may be done digitally by firstcalculating the first order low pass filter to get an averaged value,then subtracting the averaged value from the input value to get thehigh-passed value.

Still referring to aspects of the same embodiment, next, each data valueof each channel is compared to the data value from an adjacent channel,in pair-wise fashion. The largest of each pair is passed to anothercomparison, and so on, until the largest data value among the channelsis found. In instances in which more than one layer, or set, ofcomparisons in needed (e.g., in instances where at least 3 or moredigitized input signals are being compared), multiple clock periods areneeded since only one set of comparisons can be performed during eachclock period. As a result, both the data channel values and thecomparisons are pipelined.

Continuing with aspects of the same embodiment, the largest data valueamong the channels for one clock period (i.e., a largest second datavalue) is compared with the largest data value among the channels for aprevious clock period (a largest first data value). A state machine isused to compare the largest second data value to a threshold data value,which is set from another state machine. If the largest second datavalue is both greater than the threshold data value and less than thelargest first data value, a peak has been detected. It is not importantto detect the data value of the actual peak. It is sufficient for thepurposes of this embodiment of the invention to detect a data value thatis close to the data value of the actual peak. In short, this embodimentseeks a data value that is on or just after the peak.

In addition, for a peak to be found, the FPGA should be in a “find peak”state. When a peak is detected, the data values for each channel areextracted from the correct position in the pipeline of each channel andstored in a memory device, such as a first-in-first-out (FIFO) memorydevice, for later transmission to an external processor. The logic, orprogramming, then changes to a “wait to find peak” state. The logicswitches back to the “find peak” state when either the second, orcurrent, largest data value is less greater than the first, or previous,largest data value, or the current largest data value is less than thethreshold. Which of these two possibilities is used may be programmableand determined by user preferences, since they may be dependent on thenature of the signal, the overall processing problem, and/or theapplication.

FIG. 1 is a flowchart of a processing method for an FPGA that can bepart of an apparatus, such as a device that includes an FPGA, or amethod according to one embodiment of the present invention. In step101, a set of signals is received. In step 102, each of the set ofsignals may be processed, high-passed or truncated. In step 103, thechannel corresponding to the signal of highest level is determined. Thisdetermination may be done by comparing pairs of signals as detailed, forexample, in FIG. 5. At this point, the logic (e.g. a state machine) inthe FPGA is in a decrease state, and a flag holds a decreasing value.Step 104 is looped until the maximum channel value at (n) is greaterthan the maximum channel value at (n−1). When MAXn>MAX n−1, the flag isset to an increase value in step 105 (the logic assumes an increasestate) and control is passed to step 106. If the maximum channel valueat (n−1) is greater than the maximum channel value at (n) and themaximum channel value at (n) is greater than a threshold value, thechannel value at (n−2) is stored in a memory device such as, forexample, a FIFO memory in step 107. In step 108, the flag is re-set to adecreasing value and the logic assumes a decrease state. Steps 101-108are repeatable and may be performed continuously.

FIG. 2 is a spreadsheet showing a processing layout for an FPGA that canbe a part of an apparatus, such as a device that includes the FPGA, or amethod according to one embodiment of the present invention.

The following examples are included to demonstrate specific embodimentsof the present methods and apparatuses. It should be appreciated bythose of skill in the art that the techniques disclosed in the examplesthat follow represent techniques discovered by the inventor to functionwell in the practice of the invention, and thus can be considered toconstitute specific modes for its practice. However, those of skill inthe art should, in light of the present disclosure, appreciate that manychanges can be made in the specific embodiments which are disclosed andstill obtain a like or similar result without departing from the scopeof the invention.

EXAMPLE 1

FIG. 3 is a spreadsheet showing a processing layout for an FPGA that canbe a part of an apparatus, such as a device that includes the FPGA, or amethod according to one embodiment of the present invention in which 2input signals are compared. In this embodiment, as in all embodiments, aseparate source can generate each input signal.

EXAMPLE 2

FIG. 4 is a spreadsheet showing a processing layout for an FPGA that canbe a part of an apparatus, such as a device that includes the FPGA, or amethod according to one embodiment of the present invention in which 7input signals are compared. In this embodiment, as in all embodiments, aseparate source can generate each input signal. In this embodiment,pipelining of both the data values and the comparisons is illustrated incolumns 4-8. Columns 4-6 have comparisons to find the largest data valueamong the two channels, and columns 7 and 8 have the comparisons to findif a peak has occurred and if that data value corresponding to the peakdetection is greater than a threshold data value. The data values arepassed from column to column. Those data values are not changed;instead, they are simply passed to the right awaiting the decision tostore them or not in a memory buffer, which occurs out of column 8.

EXAMPLE 3

FIG. 5 is a spreadsheet showing a processing layout for an FPGA that canbe a part of an apparatus, such as a device that includes the FPGA, or amethod according to one embodiment of the present invention in which 19input signals are compared. In this embodiment, as in all embodiments, aseparate source can generate each input signal. In this embodiment,pipelining of both the data values and the comparisons is illustrated incolumns 4-10. Columns 4-8 have comparisons to find the largest datavalue among the two channels, and columns 8 and 9 have the comparisonsto find if a peak has occurred and if that data value corresponding tothe peak detection is greater than a threshold data value. The datavalues are passed from column to column. Those data values are notchanged; instead, they are simply passed to the right awaiting thedecision to store them or not in a memory buffer, which occurs out ofcolumn 10.

EXAMPLE 4

FIG. 6 is a table showing a breadboard simulation according to oneembodiment of the present invention in which 2 input signals arecompared.

FIG. 7 is a chart graphically depicting data from FIG. 6. The time step,or x-values, for lines 100, 110, 120, 130, 140, and 150 in FIG. 6 are incolumn 1 of FIG. 6. The ADC count, or y-values, for lines 100, 110, 120,130, 140, and 150 in FIG. 7 are in columns 2, 3, 10, 11, 12, and 13,respectively, of FIG. 6.

EXAMPLE 5

Shown in the computer program listing appendix (see CD) is source code,written in Very High Speed Integrated Circuit Hardware DescriptionLanguage (VHDL), that is suitable for carrying out one embodiment of theinvention. This source code is exemplary only and does not limit thescope of the claims. It simply represents one specific embodiment forcarrying out aspects of the present methods and apparatuses and isincluded for the convenience of the reader in this regard. Those ofordinary skill in the art having the benefit of this disclosure willrecognize that a wide variety of computational techniques and/ordifferent types of corresponding source code may be used in implementingthe present methods.

The invention can be included in a kit. The kit can include some, orall, of the components that compose the invention. The kit can be anin-the-field retrofit kit to improve existing systems that are capableof incorporating the invention. The kit can include software, firmwareand/or hardware for carrying out the invention. The kit can also containinstructions for practicing the invention. Unless otherwise specified,the components, software, firmware, hardware and/or instructions of thekit can be the same as those used in the invention.

All the disclosed embodiments of the invention can be made and usedwithout undue experimentation in light of this disclosure. Theindividual components described above need not be made in the exactdisclosed forms, or combined in the exact disclosed configurations, butcould be provided in any suitable form, and/or combined in any suitableconfiguration. Further, although the present methods can be practicedusing separate modules, such modules may be integrated into systems withwhich they are associated.

It will also be clear to those of ordinary skill in the art thatsubstitutions, modifications, additions and/or rearrangements of thefeatures of the inventive methods and devices may be made withoutdeviating from their scope, which is defined by the claims and theirequivalents. The appended claims are not to be interpreted as includingmeans-plus-function limitations, unless such a limitation is explicitlyrecited in a given claim using the phrase(s) “means for” and/or “stepfor,” respectively.

REFERENCES

The disclosures of the following publications in their entireties areexpressly incorporated by reference for the purpose of indicatingaspects of the state of the art.

-   Van Nostrand's Scientific Encyclopedia, 8th ed., Van Nostrand    Reinhold, (Douglas M. Considine et al. eds.), 1995.-   Marks Mechanical Engineering Handbook, 10th ed., McGraw Hill,    (Eugene A. Avallone et al. eds.), 1996.-   The Electrical Engineering Handbook, CRC Press, (Richard C. Dorf et    al. eds.), 1993.

1-19. (canceled)
 20. A detection method comprising: receiving multipledigitized input signals, each having a data value associated with it;and detecting that a peak data value has occurred using (a) comparisonsof multiple data values to each other over multiple clock periods, and(b) a threshold data value.
 21. The detection method of claim 20,further comprising: after a peak has occurred, extracting the datavalues and storing them in a memory device.
 22. The detection method ofclaim 20, further comprising: digitizing multiple analog input signals.23. The detection method of claim 20, further comprising: filtering themultiple digitized input signals.
 24. The detection method of claim 20,further comprising: receiving at least two analog input signalsseparated by an interval of no greater than 20 nanoseconds.
 25. Adetection method comprising: receiving at least two multiple digitizedinput signals, each multiple digitized input signal having a data valueassociated with it; and detecting that a peak data value has occurredusing (a) a comparison of at least two of the data values to each otherto determine which is larger, and (b) a threshold data value.
 26. Thedetection method of claim 25, further comprising: after a peak hasoccurred, extracting the data values and storing them in a memorydevice.
 27. The detection method of claim 25, further comprising:digitizing multiple analog input signals.
 28. The detection method ofclaim 25, further comprising: filtering the multiple digitized inputsignals.
 29. The detection method of claim 25, further comprising:receiving at least two analog input signals separated by an interval ofno greater than 20 nanoseconds.
 30. A field programmable gate array(FPGA) configured to at least: receive at least two multiple digitizedinput signals, each multiple digitized input signal having a data valueassociated with it; and detect that a peak data value has occurred using(a) a comparison of at least two of the data values to each other todetermine which is larger, and (b) a threshold data value.
 31. The FPGAof claim 30, where the FPGA is further configured to at least: after apeak has occurred, extract the data values and storing them in a memorydevice.
 32. The FPGA of claim 30, where the FPGA is further configuredto at least: digitize multiple analog input signals.
 33. The FPGA ofclaim 30, where the FPGA is further configured to at least: filter themultiple digitized input signals.
 34. The FPGA of claim 30, where theFPGA is configured to process at least two analog input signalsseparated by an interval of no greater than 20 nanoseconds.